The invention relates to instruction sets for processors and more particularly to a method for providing an instruction set for a processor.
General purpose processors perform functions in response to a set of instructions that form a program. This is stored in a program memory. The memory capacity required to store the program is related to the length of the instruction word and the number of instruction steps in the program.
The instructions in the program memory are used to generate parallel control signals in a decode unit that controls the operations performed by the processor. The complexity of the logic required to translate the instruction words into control is related to the length of the instruction word input to the decode unit.
In order to optimise processor performance in terms of speed and power consumption it is desirable to provide as many instructions to a software designer as possible, allowing the designer access to the full functionality of the processor.
If a fully flexible instruction word set, individually specifying each function the processor can perform is used, the designer has maximum freedom to design an optimal algorithm implementation. An efficient instruction set that allows full access to the functionality of a processor that meets future performance requirements of the telecommunications industry is far greater than 16 bits which is the current standard. For the purposes of this document a 90 bit instruction word is assumed to be suitable. Even larger instruction sets may, however, at some point be desirable resulting in even longer instruction words. With 90 bit instruction words the program memory may be as wide as 90 bits and of the order of 16 bits long to accommodate the program for implementing a typical processor algorithm for a radio telephony application.
This has the disadvantage for low cost applications that a large memory is needed to store the program as the instruction words will be 90 bits long. The interface between the program memory and the instruction decoder needs to have additional interconnects in order to allow the 90 bit instruction words to be received by the decode unit. This again adds to the size and power consumption of the processor. Finally the logic needed to implement the decode unit is increased in roughly direct proportion with the number of input pins. The decode unit is, therefore, more complex and consequently more expensive.
In battery powered consumer products where cost and power consumption are of considerable concern to the designer, a compromise needs to be made between instruction set flexibility and resulting power efficiency and instruction word length and the increased cost.
One conventional approach to resolving this conflict is to set the instruction word length by determining in advance a restricted number of instructions from which the designer is able to select. The choice of the restricted instruction set is of paramount importance and will typically be the instructions perceived to be most useful for a range of functions the processor might need to perform.
This approach has the disadvantage that if the restricted instruction set does not include a particular instruction or the building blocks of that instruction, although the processor has hardware capable of functioning in accordance with that instruction it will be unable to operate in that fashion. This can lead to design compromises that may reduce the efficiency of the device the processor is driving and make the required performance of the device controlled by the processor difficult to achieve.
If the instruction set does not include a particular instruction, it may still be possible to create the same instruction by combining a number of other instructions. This will inevitably result in more power being consumed in providing the desired performance than if the desired instruction had formed part of the restricted instruction set.